The Secure Systems and Architectures (SAS) department secures electronic components and embedded architectures against hardware and software attacks. By combining threat modeling, countermeasure design, and experimental validation, it develops innovative solutions to protect circuits, embedded systems, and critical infrastructures. Its work ensures the confidentiality, integrity, and authenticity of data by integrating security from the outset using a “secure by design” approach.

Head of Department
Olivier Potin
Email: olivier.potin@mines-stetienne.fr

33 members (researchers, engineers, and PhD students)
4 major research themes in hardware cybersecurity and microelectronics
1 research unit / joint team
+10 funded projects in collaboration with industry and academic partners

Areas of Expertise

The SAS department develops innovative approaches to protect hardware architectures and embedded systems against physical and software attacks.

Core Competencies

  • Physical attack modeling (risk and vulnerability analysis).
  • Development of hardware and software countermeasures (circuit security, embedded cryptography).
  • Securing communications and critical infrastructures.
  • Experimental validation of protections using advanced test benches.
  • “Secure by design” approach to integrate security from the design phase.

Fields of activity

  • Secure microelectronics: design of integrated circuits resistant to attacks.
  • Embedded systems and IoT: protecting connected objects against physical attack threats.
  • Smart cards and secure transactions: payment and identification technologies.
  • Cybersecurity of critical infrastructures: securing industrial and military systems.
  • Validation of electronic devices.

Research Areas

The SAS department structures its work around 4 research areas aimed at guaranteeing the security of electronic systems in the face of emerging attacks.

Securing embedded AI (Secure Embedded AI)

Objective
Understanding and countering attacks targeting artificial intelligence implementations.

Focus
Protection against model theft (model theft), training set poisoning (training set poisoning), and adversarial attacks (adversarial examples).

Partnerships & Networks
ANR PICTURE and AI.MMUNITY projects; participation in ANSSI’s SEPIA working group, part of INESIA (National Institute for AI Evaluation and Security).

Securing embedded AI (Secure Embedded AI)

Cryptography Research & Development (LWC, PQC)

Objective
Analyzing arithmetic vulnerabilities and designing new cryptographic standards adapted to hardware constraints.

Focus
Development of post-quantum cryptography (PQC), lightweight cryptography (LWC), mathematical representation of numbers, and design of dedicated arithmetic operators.

Collaborations
Industrial projects with SealSQ and Thales DIS, organization of summer schools (e.g., AfricaCrypt 2026).

Cryptography Research & Development (LWC, PQC)

Microelectronics Design: Secure Processors and Algorithms

Objective
Implementing hardware protection schemes and designing test integrated circuits for experimentation.

Focus
Design of RISC-V processors ensuring safe and secure software execution (e.g., CVA6 superscalar processor within the OpenHW Group) and test vehicles in international partnership.

Microelectronics Design: Secure Processors and Algorithms

Modeling hardware attacks for mitigation (Mitigation)

Objective
Studying and reproducing physical attack mechanisms to develop effective countermeasures and pre-silicon simulation tools.

Focus
Fault injection modeling, advanced characterization (photo-emission, TLS thermal laser stimulation), patent filing, and development of the FISIC software tool (Fault Injection Simulator for Integrated Circuits).

Focus
Fault injection modeling, advanced characterization (photo-emission, TLS thermal laser stimulation), patent filing, and development of the FISIC software tool (Fault Injection Simulator for Integrated Circuits).

Modeling hardware attacks for mitigation (Mitigation)

Scientific Excellence
Work recognized with the Best Paper Award at the IEEE HOST 2026 conference.


Research unit

The Secure Systems and Architectures (SAS) department is an essential component of the EC – SAS joint team, a joint research unit between Mines Saint-Étienne and the CEA. Its expertise in securing hardware architectures and embedded systems contributes directly to the unit’s work by modeling threats, designing innovative countermeasures, and developing experimental validation methodologies. Through its research on physical attacks (power analysis, fault injection) and the protection of electronic circuits, the SAS department enables the research unit to offer advanced security solutions adapted to current hardware cybersecurity challenges. Its “secure by design” approach, which integrates security from the system design phase, strengthens the reliability of technologies developed within the SAS joint team, in response to the needs of strategic industries and critical infrastructures.


The SAS department develops innovative solutions to anticipate threats, secure embedded architectures, and strengthen the resilience of electronic systems, meeting the challenges of strategic industries and critical infrastructures.

Contact and Practical Information

  • Address
    École des mines de Saint-Étienne
    Centre of Microelectronics in Provence
    880, route de Mimet
    13541 Gardanne, France
  • Transportation
    Bus
    Line 183, “Centre Charpak” stop
    Train
    From Gardanne station, regular shuttles via line 3
    Airport
    Connections from Marseille Provence Airport