PIC
Bruno Robisson
Head of Secure Architectures and Systems Department
Joint team CEA / Ecole des Mines de Saint-Etienne

1 Contact information

Adress : Centre de Microélectronique de Provence, 880 route de Mimet, 13541 Gardanne, France

E-mail : my_first_name.my_name@cea.fr

Phone : +33(0)442616731

Web page  : http ://www.mines-stetienne.fr/~robisson/

Data bases : linkedin, Google Scholar, Research gate, Microsoft Academic Search,HAL,dblp

2 Experience

3 Education

4 Scientic activities

Skill and expertise

PhD students

5 Teaching

6 Publications and Communications

Book chapters :

[1]   Traité de la carte à puce, Hermès, 2013, Ch. Chapitre Attaques physiques, pp. 135–171.
URL http://www.lavoisier.fr/livre/notice.asp?ouvrage=2745320

Articles :

[2]   D. Aboulkassimi, J. Fournier, L. Freund, B. Robisson, A. Tria, EMA as a physical method for extracting secret data from mobile phones, International Journal of Computer Science and Applications (IJCSA) 2 (1) (2013) 16–25.
URL http://www.ij-csa.org/Download.aspx?ID=2542

[3]   J. Fournier, J.-B. Rigaud, S. Bouquet, B. Robisson, A. Tria, J.-M. Dutertre, M. Agoyan, Design and characterisation of an AES chip embedding countermeasures, International Journal of Intelligent Engineering Informatics (IJIEI) 1 (3-4) (2011) 328–347.
URL http://dx.doi.org/10.1504/IJIEI.2011.044101

Invited talks :

[4]   J.-M. Dutertre, J. Fournier, A.-P. Mirbaha, D. Naccache, J.-B. Rigaud, B. Robisson, A. Tria, Review of fault injection mechanisms and consequences on countermeasures design, in : International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2011, pp. 1–6.
URL http://dx.doi.org/10.1109/DTIS.2011.5941421

[5]   A. Tria, B. Robisson, J.-M. Dutertre, A.-P. Mirbaha, Fault attacks : What is possible to do !, in : Workshop on Foundations and Practice of Security (MITACS), 2009.
URL http://www-mitacs2009.imag.fr/Material/mitac_part1.pdf

[6]   B. Robisson, Conception de circuits sécurisés : Nécessité de prendre en compte les fautes, in : Colloque national Groupement De Recherche SoC-SiP, 2007.
URL http://www.mines-stetienne.fr/~robisson/robisson_2007_methodes_de_conception_securisee_contre_faute.pdf

[7]   B. Robisson, A. Tria, Méthodes de conception sécurisée contre les attaques en faute, in : Journées de la section électronique du club EEA "SiP et SoC :nouvelles perspectives, nouveaux défis", 2007.

[8]   B. Robisson, A. Tria, Safe design methodologies against fault attacks, in : Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2006.
URL http://conferenze.dei.polimi.it/FDTC06/zzz%20Robisson.pdf

Papers with proceedings :

[9]   H. Le Bouder, S. Guilley, B. Robisson, A. Tria, Fault injection to reverse engineer des-like cryptosystems, in : To appear in 6th International Symposium on Foundations and Practice of Security (FPS), 2013.

[10]   K. Heydemann, N. Moro, E. Encrenaz, B. Robisson, Formal verification of a software countermeasure against instruction skip attacks, in : PROOFS 2013, Santa-Barbara, États-Unis, 2013.
URL http://hal-emse.ccsd.cnrs.fr/emse-00869509

[11]   N. Moro, A. Dehbaoui, K. Heydemann, B. Robisson, E. Encrenaz, Electromagnetic fault injection : towards a fault model on a 32-bit microcontroller, in : 10th workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2013, pp. 77–87.
URL http://dx.doi.org/10.1109/FDTC.2013.9

[12]   I. Exurville, J. Fournier, J.-M. Dutertre, B. Robisson, A. Tria, Practical measurements of data path delays for IP authentication and integrity verification, in : 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) , 2013, pp. 1–6.
URL http://dx.doi.org/10.1109/ReCoSoC.2013.6581551

[13]   A. Dehbaoui, J.-M. Dutertre, B. Robisson, A. Tria, Investigation of near-field pulsed EMI at IC level, in : Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility (APEMC), 2013, pp. 185–188.
URL http://search.informit.com.au/documentSummary;dn=445162872344532;res=IELENG

[14]   L. Zussa, J.-M. Dutertre, J. Clédière, B. Robisson, A. Tria, Investigation of timing constraints violation as a fault injection means, in : Conference on Design of Circuits and Integrated Systems (DCIS), 2012, pp. 1–6.

[15]   B. Robisson, H. Le Bouder, J.-M. Dutertre, A. Tria, A unified formalism for side-channel and fault attacks on cryptographic circuits, in : Conference on Design of Circuits and Integrated Systems (DCIS), 2012, pp. 7–9.

[16]   A. Dehbaoui, J.-M. Dutertre, B. Robisson, A. Tria, Electromagnetic transient faults injection on a hardware and a software implementations of AES, in : Fault Diagnosis and Tolerance in Cryptography (FDTC), 2012, pp. 7 –15.
URL http://dx.doi.org/10.1109/FDTC.2012.15

[17]   R. Lashermes, G. Reymond, J.-M. Dutertre, J. Fournier, B. Robisson, A. Tria, A DFA on AES based on the entropy of error distributions, in : Fault Diagnosis and Tolerance in Cryptography (FDTC), 2012, pp. 34 –43.
URL http://dx.doi.org/10.1109/FDTC.2012.18

[18]   P. Bayon, L. Bossuet, A. Aubert, V. Fischer, F. Poucheret, B. Robisson, P. Maurine, Contactless electromagnetic active attack on ring oscillator based true random number generator, in : W. Schindler, S. Huss (Eds.), Constructive Side-Channel Analysis and Secure Design (COSADE), Vol. 7275 of Lecture Notes in Computer Science, Springer Berlin / Heidelberg, 2012, pp. 151–166.
URL http://dx.doi.org/10.1007/978-3-642-29912-4\_12

[19]   D. Aboulkassimi, M. Agoyan, L. Freund, J. Fournier, B. Robisson, A. Tria, Electromagnetic analysis (EMA) of software AES on Java mobile phones, in : IEEE International Workshop on Information Forensics and Security (WIFS), 2011, pp. 1–6.
URL http://dx.doi.org/10.1109/WIFS.2011.6123131

[20]   M. H. Nguyen, B. Robisson, M. Agoyan, N. Drach-Temam, Low-cost recovery for the code integrity protection in secure embedded processors, in : IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2011, pp. 99 –104.
URL http://dx.doi.org/10.1109/HST.2011.5955004

[21]   M. Doulcier-Verdier, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, B. Robisson, A. Tria, A side-channel and fault-attack resistant AES circuit working on duplicated complemented values, in : IEEE International Conference on Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, pp. 274–276.
URL http://dx.doi.org/10.1109/ISSCC.2011.5746316

[22]   F. Poucheret, L. Chusseau, B. Robisson, P. Maurine, Local electromagnetic coupling with CMOS integrated circuits, in : International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2011, pp. 137–141.
URL http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=6130082

[23]   F. Poucheret, K. Tobich, M. Lisart, L. Chusseau, B. Robisson, P. Maurine, Local and direct EM injection of power into CMOS integrated circuits, in : Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2011, pp. 100–104. doi:10.1109/FDTC.2011.18.
URL http://dx.doi.org/10.1109/FDTC.2011.18

[24]   B. Robisson, M. Agoyan, S. Bouquet, M.-H. Nguyen, S. L. Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan-Sabet, N. Drach-Temam, Management of the security in smart secure devices, in : International Conference on Smart System Integration (SSI), 2011, pp. 1–9.
URL http://www.emse.fr/~robisson/article\_SOS\_SSI.pdf

[25]   M. Agoyan, S. Bouquet, M. Doulcier-Verdier, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, B. Robisson, A.Tria, Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key, in : International Conference on Smart System Integration (SSI), 2011, pp. 10–14.
URL http://www.emse.fr/~robisson/article\_AES\_SSI.pdf

[26]   B. Robisson, M. Agoyan, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan-Sabet, Implementation of complex strategies of security in secure embedded systems, in : IFIP International Conference on New Technologies, Mobility and Security (NTMS), 2011, pp. 1–5.
URL http://dx.doi.org/10.1109/NTMS.2011.5721145

[27]   J.-B. Rigaud, J.-M. Dutertre, M. Agoyan, B. Robisson, A. Tria, Experimental fault injection around the prototyping of an AES cryptosystem, in : International Workshop on Reconfigurable Communication-centric Systems on Chip (ReCoSoc), 2010, pp. 141–147.
URL http://hal-emse.ccsd.cnrs.fr/emse-00505355/en/

[28]   M. Agoyan, J.-M. Dutertre, D. Naccache, B. Robisson, A. Tria, When clocks fail : On critical paths and clock faults, in : D. Gollmann, J.-L. Lanet, J. Iguchi-Cartigny (Eds.), Smart Card Research and Advanced Application Conference (CARDIS), Vol. 6035 of Lecture Notes in Computer Science, Springer, 2010, pp. 182–193.
URL http://dx.doi.org/10.1007/978-3-642-12510-2\_13

[29]   M. H. Nguyen, B. Robisson, M. Agoyan, N. Drach, Low-cost fault tolerance on the ALU in simple pipelined processors, in : International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010, pp. 28 –31.
URL http://dx.doi.org/10.1109/DDECS.2010.5491822

[30]   M. H. Nguyen, B. Robisson, M. Agoyan, N. Drach-Temam, Evaluation of the time-redundant fault tolerance on the ALU for simple pipelined processor, in : Austin Conference on Integrated Systems and Circuits (ACISC), 2009, pp. 1–4.

[31]   S. Laabidi, B. Robisson, M. Agoyan, An evaluation methodology for the security of cryptosystems, in : IEEE "Ph.D Research in Microelectronics and Electronics" (PRIME), 2008, pp. 113–115.
URL http://dx.doi.org/10.1109/RME.2008.4595738

[32]   B. Robisson, P. Manet, Differential behavioral analysis, in : P. Paillier, I. Verbauwhede (Eds.), Cryptographic Hardware and Embedded Systems (CHES), Vol. 4727 of Lecture Notes in Computer Science, Springer, 2007, pp. 413–426.
URL http://dx.doi.org/10.1007/978-3-540-74735-2\_28

[33]   T.-H. Le, J. Clédière, C. Canovas, B. Robisson, C. Servière, J.-L. Lacoume, A proposition for correlation power analysis enhancement, in : L. Goubin, M. Matsui (Eds.), Cryptographic Hardware and Embedded Systems (CHES), Vol. 4249 of Lecture Notes in Computer Science, Springer, 2006, pp. 174–186.
URL http://dx.doi.org/10.1007/11894063\_14

[34]   P. Manet, J.-B. Rigaud, J. Francq, M. Jeambrun, A. Tria, B. Robisson, J. Quartana, S. Laabidi, Integrated evaluation platform for secured devices, in : International Workshop on Reconfigurable COmmmunication-centric System On Chip (ReCoSoc), 2006, pp. 214–219.
URL http://www.researchgate.net/publication/221636768_Integrated_Evaluation_Platform_for_Secured_Devices/file/79e41512fcd8fe1627.pdf

[35]   F. Bouesse, M. Renaudin, B. Robisson, E. Beigné, P.-Y. Liardet, S. Prevosto, DPA on quasi delay insensitive asynchronous circuits : concrete results, in : Conference on Design of Circuits and Integrated Systems (DCIS), 2004, pp. 1–6.

[36]   B. Robisson, J.-G. Ganascia, An algorithm for converting an electrical circuit to a bond graph : a formalization of the inspection method, in : J. Granda, G. Dauphin-Tanguy (Eds.), International Conference on Bond Graph Modeling and Simulation (ICBGM), Vol. 33 of Simulation Series, 2001, pp. 199–203.
URL http://www.mines-stetienne.fr/~robisson/robisson_2001_algorithm_for_converting_electrical_circuit_to_a_bond_graph_ICBGM.pdf

[37]   B. Robisson, J.-G. Ganascia, Découverte scientifique et électronique de puissance : Un algorithme de génération utilisant les graphes de liens, in : C. De La Higuera (Ed.), Colloque Français d’Apprentissage (CAP), Hermès, 2000, pp. 235–244.

[38]   B. Robisson, J.-G. Ganascia, On the representation of electrical networks, in : IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Vol. 1, 2000, pp. 144–147.
URL http://dx.doi.org/10.1109/MWSCAS.2000.951606

[39]   B. Robisson, J.-G. Ganascia, Computing a canonical bond graph from a component-connection representation, in : W. F. Waite (Ed.), Summer Computer Simulation Conference (SCSC), SCS, 2000, pp. 109–113.

Communications :

[40]   H. Le Bouder, B. Robisson, A. Tria, Formalisme des attaques physiques, in : Colloque Crypto’Puces, 2013.

[41]   B. Robisson, H. Le Bouder, A. Tria, A Unified Formalism for Side-Channel and Fault Attacks on Cryptographic Circuits , in : Chip-to-Cloud Security Forum, 2013.

[42]   H. Le Bouder, S. Guilley, B. Robisson, A. Tria, Fault Injection to Reverse Engineer DES-like Cryptosystems , in : Chip-to-Cloud Security Forum, 2013.

[43]   N. Moro, A. Dehbaoui, K. Heydemann, B. Robisson, E. Encrenaz, Electromagnetic fault injection on microcontrollers, in : Chip-to-Cloud Security Forum , 2013.
URL http://hal-emse.ccsd.cnrs.fr/emse-00871686

[44]   J. Fournier, B. Robisson, Hardware integrity : from design to characterisation, in : LETI Innovation Days, 2013.
URL http://www.leti-innovationdays.com/presentations/AnnualReview/J2SessionA/A12_J%20Fournier_Hardware%20integrity_LETI_Innov_Days_June_13_SAS_FINAL.pdf

[45]   B. Robisson, I. Exurville, J.-Y. Zie, H. Le Bouder, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, The bad and the good of physical functions, in : Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi), 2013.

[46]   P. Bayon, L. Bossuet, A. Aubert, V. Fischer, F. Poucheret, B. Robisson, P. Maurine, Contactless electromagnetic active attack on ring oscillator based true random number generator, in : International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi), 2012.

[47]   P. Maurine, A. Dehbaoui, F. Poucheret, J. Dutertre, B. Robisson, A. Tria, On the use of the electromagnetic medium as a fault injection means, in : International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi), 2012.

[48]   F. Poucheret, K. Tobich, B. Robisson, P. Maurine, Injection directe de puissance par médium EM : Un moyen de perturber les circuits intégrés ?, in : Journée "sécurité numérique" du Groupement De Recherche SoC-SiP, 2011.
URL http://www2.lirmm.fr/journees_securite/material/j4/Poucheret.pdf

[49]   P. Bayon, L. Bossuet, A. Aubert, V. Fischer, F. Poucheret, B. Robisson, P. Maurine, Contactless EM fault attack in ring oscillators based TRNG, in : International Workshop on Practical Hardware Innovations in Security Implementation and Characterisation (PHISIC), 2011.

[50]   B. Robisson, M. Agoyan, P. Bazargan-Sabet, K. Bekkou, S. Bouquet, S. Le Henaff, E. Lepavec, M.-H. NGuyen, G. Phan, P. Soquet, F. Wajsbürt, Smart On Smart, in : ANR workshop on "Systèmes embarqués, sécurité et sûreté de fonctionnement, 2010.

[51]   M. Agoyan, B. Robisson, M.-H. Nguyen, P. Bazargan-Sabet, S. Phan, G.and Le Henaff, Smart On Smart : An innovative architecture, in : International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi), 2010.

[52]   P. Soquet, B. Robisson, M. Agoyan, G. Phan, P. Bazargan-Sabet, F. Wajsbürt, Strategy Of Security in Smart On Smart, in : Workshop PACA Security Trends In embedded Security (PASTIS), 2010.

[53]   J.-M. Dutertre, A.-P. Mirbaha, A. Tria, B. Robisson, M. Agoyan, Revue expérimentale des techniques d’injection de fautes, in : Journée "sécurité numérique" du Groupement De Recherche SoC-SiP, 2010.
URL http://www2.lirmm.fr/journees_securite/material/j2/Dutertre.pdf

[54]   J.-M. Dutertre, A. Tria, B. Robisson, M. Agoyan, Low cost fault injection method for security characterization, in : Conference E-Smart, 2009.

[55]   J.-M. Dutertre, A. Tria, B. Robisson, Injection de fautes par modification de l’horloge : Application à l’AES, in : Crypto’puces, 2009.

[56]   S. Laabidi, B. Robisson, A. Tria, An evaluation methodology for the security of cryptosystems, in : Conference E-Smart, 2008.

[57]   A. Tria, B. Robisson, S. Laabidi, P. Manet, Differential behavioral analysis : Application to an asynchronous crypto-processor, in : USE-IT Conference, 2008.

[58]   B. Robisson, A. Tria, P. Manet, A.-L. Ribotta, Mutualized security caracterization platform for teaching, research and development, in : International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi), 2008.

[59]   B. Robisson, E. Beigné, F. Bouesse, M. Renaudin, Improvement of smart card security with asynchronous logic chips, in : Rencontres internationales des micro et nanotechnologies (MINATEC), 2003.

Posters :

[60]   H. Le Bouder, B. Robisson, N. Moro, E. Encrenaz, A. Tria, Un formalisme commun aux attaques par canaux auxiliaires et par injection de fautes, in : Poster session Journées Nationales du GDR SOC-SIP, 2012.

[61]   N. Moro, B. Robisson, E. Encrenaz, Complex security policies, in : Poster session of International Workshop on Practical Hardware Innovations in Security Implementation and Characterisation (PHISIC), 2011.

[62]   B. Robisson, Smart On Smart, in : Poster session of Workshop PACA Security Trends In embedded Security (PASTIS), 2010.

[63]   B. Robisson, M. Agoyan, Smart On Smart, in : Poster session of Workshop ANR-STIC, 2010.

[64]   M.-H. Nguyen, M. Agoyan, P. Manet, B. Robisson, Test d’intégrité de code couplée à de la compression, in : Poster session of Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM), 2008.

[65]   S. Laabidi, B. Robisson, Outils de conception dédiés à la sécurisation des circuits cryptographiques, in : Poster session of Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM), 2007.

Others :

[66]   K. Heydemann, N. Moro, E. Encrenaz, B. Robisson, Formal verification of a software countermeasure against instruction skip attacks, Cryptology ePrint Archive, Report 2013/679 (Octobre 2013).
URL http://eprint.iacr.org/2013/679

[67]   A. Dehbaoui, J. Dutertre, B. Robisson, P. Orsatelli, P. Maurine, A. Tria, Injection of transient faults using electromagnetic pulses - Practical results on a cryptographic system, Cryptographic eprint archives, Reference 2012/123 (Februar 2012).
URL http://eprint.iacr.org/2012/123.pdf

[68]   B. Robisson, Simulation qualitative des circuits de l’électronique de puissance, Master thesis, Université Pierre et Marie Curie, Paris, France (September 1998).

[69]   B. Robisson, Découverte automatique de circuits en électronique de puissance, Phd thesis, Université Pierre et Marie Curie, Paris, France (21 September 2001).
URL http://tel.archives-ouvertes.fr/docs/00/04/76/49/PDF/tel-00008279.pdf

7 Hobbies